1. Field of the Invention
The present invention relates to an automatic trace shaping method and an automatic trace shaping apparatus for automatically shaping existing traces consisting of straight and/or curved lines that are designed to be disposed in arbitrary directions, on a surface of a substrate of a semiconductor package, into traces each consisting of a combination of segments in predetermined directions by using computation.
2. Description of the Related Art
In LSI (Large-scale integration), PCB (Printed-circuit board) and the like as manufacturing, for example, set forth in Jono, “An operating method of an integrated printed-circuit board CAD tool”, Design Wave Magazine, CQ Publishing Co., Ltd., June 2003, pp. 51-56, it is typical that a trace is comprised of a plurality of straight line segments and the trace is designed so that these segments lie in directions of 90 or 45 degrees with respect to a predetermined reference line. In the LSI and the PCB that have pattern characteristics in that there are relatively large spaces around the traces and disposed positions and shapes of obstacles have certain regularity, the traces in the LSI, the PCB and the like can be easily designed according to design rules that allow computation by a computer and, therefore, several automatic wiring methods have already been proposed.
For example, as a typical example of the automatic wiring methods for the LSI and the PCB, there is a method called a labyrinth search method as set forth in Japanese Unexamined Patent Publication No. 11-161694, Japanese Unexamined Patent Publication No. 2001-350813, Japanese Unexamined Patent Publication No. 2001-044288, and Japanese Unexamined Patent Publication No. 10-209288. In this labyrinth search method, trace routes on a substrate are set so as to secure clearance from obstacles and so as not to intersect the obstacles by bypassing such obstacles in the directions of 90 degrees or, in some cases, 45 degrees.
In contrast to this, on substrates of semiconductor integrated circuit mounting packages (hereinafter simply referred to as the “semiconductor packages”) such as PBGA, EBGA and the like, there exist a large number of elements, such as planes, gates, marks, internal components or other traces in the packages and so on that may obstruct the traces and shapes and the disposed positions or angles of such obstacles may vary significantly. Further, vias, balls, bonding pads (B/P), flip chip pads (F/C) or the like, which are to be starting or end points of the traces, may be positioned variously and, moreover, sufficient spaces often cannot be secured around the traces. Therefore, in trace design of the semiconductor packages, traces are often disposed in directions of arbitrary angles on the surface of the substrate of the semiconductor package. In the trace design of the semiconductor packages, a designer typically designs the trace routes of the semiconductor packages on a virtual plane by trial and error depending on the designer's skill, experience and intuition and, for example, by using a CAD system.
As a trace design method of the semiconductor packages, for example, Japanese Unexamined Patent Publication No. 2002-083006 describes an automatic wiring method that uses a CAD system for generating, by automatic computation, trace shapes satisfying design rules, for example, by generating circular arcs around vias according to the design rules and combining the traces based on tangents of the circular arcs.
Further, for example, Japanese Unexamined Patent Publication No. 09-069118 describes a semi-automatic wiring method that does not rely on automatic computation but generates an outlined route manually and determines an optimal route when semiconductor elements other than two or more semiconductor elements between which a trace route is intended to be set are assumed to be obstacles.
Still further, for example, Japanese Unexamined Patent Publication No. 05-055305 describes a trace design method of semiconductor packages that implements traces in directions of specific angles.
As described above, when the traces in arbitrary directions (at arbitrary angles), that is to say, for example, the traces comprised of straight and/or curved lines, are designed in the semiconductor packages, a CAD for the semiconductor packages that complies with such trace design is typically used. In contrast to this, a CAD for the LSI is good at designing the traces each consisting of a combination of segments in the direction of “45×n” degrees (where n is an integer) with respect to a predetermined reference line (hereinafter also referred to as the “45-degree traces” or the “inclined 45-degree traces”) but weak in designing the traces in the arbitrary directions and the curved traces. In other words, there is no compatibility between trace design data designed by the CAD for the semiconductor packages and that designed by the CAD for the LSI. In reality, the traces in the circuit boards are often designed by using the CAD for the LSI and, in this case, even though the trace design for the semiconductor packages has already been completed, the traces have to be redesigned so that the trace design can be utilized also in the CAD for the LSI.
Further, in order to implement the 45-degree traces described above by using the CAD for the semiconductor packages, the designer has to set the direction in which the traces can be disposed at 45 degrees on the CAD software for the semiconductor packages and, then, while viewing a display screen, has to manually design each segment or each trace one by one by trial and error so as to satisfy requirements for clearance (lines and spaces). Traces on the surface of the substrate of the semiconductor packages are very dense and it is difficult to secure the sufficient spaces around the traces and, therefore, it has to be said that it is difficult, in itself, to implement the 45-degree traces.
In the manual trace design by trial and error as described above, as the required traces become more complicated, the effort, time and difficulty for achieving the optimal traces is increased. Further, unevenness in quality of finished products in which the traces have been designed is also increased. In reality, because the manual trace design by trial and error requires about 3-10 days for one product and it is not economical to waste further time for trace designing, the designer has to compromise with a certain design quality.
In view of the above problems, it is an object of the present invention to provide an automatic trace shaping method and an automatic trace shaping apparatus that can automatically shape existing traces consisting of straight and/or curved lines that are designed to be disposed in arbitrary directions on a surface of a substrate of a semiconductor package into traces each consisting of a combination of only segments having specific angles with respect to a predetermined reference line.